Thank you to the following supporters of ICASSP 2007
Tuesday, April 17, 10:30 to 12:30, Room 301B
Presented by Chris Eddington
There is a wide range of cost/performance tradeoffs for implementing DSP algorithms into silicon, especially when targeting diverse technologies like FPGAs and ASICs. Finding the optimal implementation usually involves exploring parallel vs. serial architectures and will be highly dependent on the available resources, speed, and architecture of the technology. This session will explore how some of the commmonly used optimizations work and how they can be applied automatically to high-level algorithm models using Synplicity's Synplify DSP tool. The seminar will include examples in wireless communications and will benefit engineers who are interested in:
Chris Eddington, Technical Marketing Manager DSP Products, Synplicity Inc.
Chris is responsible for product marketing, definition, and strategy for DSP products at Synplicity. Prior to working at Synplicity he has held a variety of IC design and technical marketing positions in the semiconductor and aerospace industries, including Mellanox Technologies, 8x8 Inc., and JPL/NASA. He has successfully developed and supported DSP-based products in wireless communications, video conferencing, and high performance networking. Chris holds a MSEE in Signal and Image Processing from the University of Southern California.