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Thank you to the following supporters of ICASSP 2007

Xilinx - DSP Design Flow Workshop

Friday, April 20 and Saturday, April 21, 09:00 - 17:00 (both days)
Presented by Jeff Weintraub at the University of Hawaii, Holmes Hall Room 387

Note about Workshop: This workshop is being held at the University of Hawaii, not the ICASSP 2007 venue. Transportation is not provided, but it is a short taxi or bus ride from the Hawaii Convention Center. Bus information can be found at http://www.thebus.org/. Take the Route A Express to the University of Hawaii Campus. The University of Hawaii workshop lab is inside the campus Holmes Hall 387 (Holmes Hall at the intersection between Dole Street and East-west road).

• PDF Map of Route A Bus Line
• PDF Map of University of Hawaii Campus

Course Description

This is a two day XUP Workshop offering hands-on training FREE of charge. The University of Hawaii will be providing the facility and the computers. Transportation to University of Hawaii is not provided; Attendees are responsible for their own transportation.

Attendees receive $1,500 worth of technical training plus over $2,500 worth of software Tools for attending the workshop.

XUP will be providing the certified trainer, boards and software for the workshop, materials, and catering for the two days.

The DSP Design Flow workshop provides an introduction to the advanced tools you need to design and implement DSP algorithms targeting FPGAs. This intermediate workshop in implementing DSP functions focuses on learning how to use System Generator for DSP, as well as HDL design flow, CORE Generator software, and design implementation tools. Through hands-on exercises, you will implement a design from algorithm concept to verification.

Prerequisites

• Fundamentals of MATLAB/Simulink and Xilinx FPGAs
• Basics of digital signal processing theory for functions such as FIR (Finite Impulse Response) filters

Workshop Goals

• Learn how to implement a DSP design without having to be an FPGA expert
• Become comfortable using System Generator to develop lectures & labs, or implement research projects.

Skills Gained

• Understand the strengths and weaknesses of three design flows (HDL, CORE Generator, System Generator)
• Make a decision regarding which design flow is more appropriate based on needs and FPGA expertise
• Understand the impact of some decisions made in the Simulink environment based on the resulting size of the FPGA design
• Debug and optimize a design in the Simulink environment

Course Outline

Day 1 Agenda	Day 1 Materials
Introduction	01intro.ppt
DSP Design Flows in FPGA	02flows.ppt
Lab 1: Creating a 12x8 MAC using System Generator for DSP	11lab01.doc (lab 1 instructions)/labs/lab1 (lab 1 “user” directory)/labsolutions/lab1 (lab 1 solutions)
Lab 2: MAC FIR Filter Verification using HDL Co-Simulation	12lab02.doc (lab 2 instructions)/labs/lab2 (lab 2 “user” directory)/labsolutions/lab1 (lab 1 solutions)
Digital Filters	03filters.ppt
Lab 3: Designing an FIR filter	13lab03.doc (lab 3 instructions)
Day 2 Agenda	Day 2 Materials
Looking under the hood	04hood.ppt
Lab 4: Looking under the hood	14lab04.doc (lab 4 instructions)
Controlling the system	05control.ppt
Lab 5: Controlling the system	15lab05.doc (lab 5 instructions)
Multi-rate systems	06multirate.ppt
Lab 6: Designing a MAC FIR	16lab06.doc (lab 6 instructions)

Lab Description

• Lab 1: Brief introduction to Simulink; Overview of quantization and overflow; Create a 12 X 8 MAC using System Generator for DSP
• Lab 2 : Generate an HDL function using Core Generator; Import the function into System Generator for DSP using the black box block; Perform HDL co-simulation using the ISE Simulator; Test the function in hardware on the XUP board via JTAG co-simulation
• Lab 3: Use the FDA Tool to generate coefficients for a low-pass filter; implement low-pass filter using DA FIR filter block from System Generator; simulate with white noise and test in hardware via JTAG co-simulation
• Lab 4: Observe the effects in hardware when changing quantization and overflow parameters
• Lab 5: Create an address generator using 1) basic System Generator blocks, and 2) m-code block
• Lab 6: Using the design in lab 5, you will create a 92-tap MAC based FIR filter; you will simulate the filter with white noise and verify in hardware via JTAG co-simulation